The present invention relates to testing a semiconductor integrated circuit, and, more particularly, to an at speed test apparatus and method for a data cache included in the semiconductor integrated circuit.
As semiconductor processes have developed, system on chip (SOC) devices, in which a Central Processing Unit (CPU) and a cache memory are integrated into a single chip, have improved. Upon integrating the CPU and the cache memory by means of the single chip, data input/output speed may be improved, thereby also improving the entire performance in the CPU. However, the semiconductor integrated circuit can be defective due to a fluctuation of a manufacturing process. To detect such defects, an at speed test, which performs testing conforming to a real operation speed of the semiconductor integrated circuit, is widely used.
Operation frequency of a tester for an at speed test having about 80 MHz has been widely used. Operation frequency of the semiconductor integrated circuit may range from 100 MHz to 1 GHz. A high speed tester of an operation frequency higher than 300 MHz is suggested but may be very expensive. Even if the high speed tester is used, the operation frequency of the high speed tester may be affected by parasitic capacitance between pins or existing between a plurality of external pins, namely, external terminals for connecting the semiconductor integrated circuit to the high speed tester.
To solve such problems, the semiconductor integrated circuit may perform a high speed test and transfer the high speed test results to a low speed tester for confirmation using a high speed internal on-chip phase-locked loop (PLL) clock. Test patterns can be stored in an off-chip memory, which may be located outside of the semiconductor integrated circuit, or an on-chip memory, which may be located inside of the semiconductor integrated circuit. To perform the at speed test without deteriorating performance of a system, it is generally preferred to use the on-chip memory rather than the off-chip memory.
An exemplary technique of performing an at speed test by a tester inside an integrated circuit by itself using test patterns previously stored in an on-chip memory and transferring the testing performance results to an external low speed tester is disclosed in Japanese Patent Laid-Open Publication No. 2003-139818. To sufficiently test an operation of an area in front of a data cache in the testing method, an on-chip memory having a size larger than that of the data cache should be mounted in the integrated circuit. This causes a size of the semiconductor integrated circuit to increase and the integration density to decrease.